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DS1339 I C Serial Real-Time Clock
2
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GENERAL DESCRIPTION
The DS1339 serial real-time clock (RTC) is a lowpower clock/date device with two programmable timeof-day alarms and a programmable square-wave output. Address and data are transferred serially 2 through an I C* bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1339 has a built-in powersense circuit that detects power failures and automatically switches to the backup supply, maintaining time and date operation.
FEATURES
Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with LeapYear Compensation Valid Up to 2100 Available in a Surface-Mount Package with an Integrated Crystal (DS1339C) 2 I C Serial Interface Two Time-of-Day Alarms Programmable Square-Wave Output Oscillator Stop Flag Automatic Power-Fail Detect and Switch Circuitry Trickle-Charge Capability Underwriters Laboratory (UL) Recognized
APPLICATIONS
Handhelds (GPS, POS Terminals) Consumer Electronics (Set-Top Box, Digital Recording, Network Appliance) Office Equipment (Fax/Printers, Copier) Medical (Glucometer, Medicine Dispenser) Telecommunications (Routers, Switches, Servers) Other (Utility Meter, Vending Machine, Thermostat, Modem)
Pin Configurations appear at end of data sheet. *I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
ORDERING INFORMATION
PART DS1339C-2 DS1339C-2+ DS1339C-3 DS1339C-3+ DS1339C-33 DS1339C-33+ DS1339U-2 DS1339U-3 DS1339U-3+ DS1339U-33 DS1339U-33+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C VOLTAGE (V) 2.0 2.0 3.0 3.0 3.3 3.3 2.0 3.0 3.0 3.3 3.3 PIN-PACKAGE 16 SO (300 mils) 16 SO (300 mils) 16 SO (300 mils) 16 SO (300 mils) 16 SO (300 mils) 16 SO (300 mils) 8 mSOP 8 mSOP 8 mSOP 8 mSOP 8 mSOP TOP MARK* DS1339C-2 DS1339C-2 DS1339C-3 DS1339C-3 DS1339C-33 DS1339C-33 1339 ##-2 1339 ##-3 1339 ##-3 1339 ##-33 1339 ##-33
+ Denotes a lead-free/RoHS-compliant device. ## = second line, revision code 2 = 2.0V (VCC 10%) 3 = 3.0V (VCC 10%) 33 = 3.3V (VCC 10%) * A "+" on the top mark indicates a lead-free device.
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground........................................................................-0.3V to +6.0V Operating Temperature Range...(Noncondensing).................................................................-40C to +85C Storage Temperature Range............................................................................................-55C to +125C Soldering Temperature Range.............See precautions in the Handling, PC Board Layout, and Assembly section.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C) (Note 1) PARAMETER Supply Voltage Backup Supply Voltage Pullup Resistor Voltage (SQW/INT, SDA, SCL), VCC = 0V Logic 1 Logic 0 SYMBOL VCC VBACKUP VPU VIH VIL DS1339-2 Power-Fail Voltage VPF DS1339-3 DS1339-33 0.7 x VCC -0.5 1.58 2.45 2.70 1.70 2.59 2.85 CONDITIONS DS1339-2 DS1339-3 DS1339-33 MIN 1.8 2.7 2.97 1.3 TYP 2.0 3.0 3.3 3.0 MAX 2.2 3.3 3.63 3.7 5.5 VCC + 0.5 +0.3 x VCC 1.80 2.70 2.97 V V V V V V UNITS
DC ELECTRICAL CHARACTERISTICS
(VCC = MIN to MAX, TA = -40C to +85C.) (Note 1) PARAMETER Input Leakage I/O Leakage Logic 0 Out VOL = 0.4V; VCC > VCC MIN (-3, -33); VCC 2.0V (-2) Logic 0 Out VOL = 0.2 (VCC); 1.8V < VCC < 2.0V (DS1339-2) Logic 0 Out VOL = 0.2 (VCC); 1.3V < VCC < 1.8V (DS1339-2) VCC Active Current VCC Standby Current SYMBOL ILI ILO IOL CONDITIONS (Note 2) (Note 3) (Note 3) MIN TYP MAX 1 1 3 UNITS mA mA mA
IOL
(Note 3)
3
mA
IOL ICCA ICCS
(Note 3) (Note 4) (Note 5) 80
250 450 150
mA mA mA
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DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = MIN to MAX, TA = -40C to +85C.) (Note 1) PARAMETER Trickle-Charger Resistor Register 10h = A5h, VCC = Typ, VBACKUP = 0V Trickle-Charger Resistor Register 10h = A6h, VCC = Typ, VBACKUP = 0V Trickle-Charger Resistor Register 10h = A7h, VCC = Typ, VBACKUP = 0V VBACKUP Leakage Current SYMBOL R1 R2 R3 IBKLKG CONDITIONS MIN TYP 250 2000 4000 25 100 MAX UNITS W W W nA
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40C to +85C.) (Note 1) PARAMETER VBACKUP Current EOSC = 0, SQW Off VBACKUP Current EOSC = 0, SQW On VBACKUP Current EOSC = 1 SYMBOL IBKOSC IBKSQW IBKDR CONDITIONS (Note 6) (Note 6) (Note 6) MIN TYP 400 600 10 MAX 700 1000 100 UNITS nA nA nA
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AC ELECTRICAL CHARACTERISTICS
(VCC = MIN to MAX, TA = -40C to +85C.) (Note 12) PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition (Note 7) LOW Period of SCL Clock HIGH Period of SCL Clock Setup Time for a Repeated START Condition Data Hold Time (Notes 8, 9) Data Setup Time (Note 10) Rise Time of Both SDA and SCL Signals (Note 11) Fall Time of Both SDA and SCL Signals (Note 11) Setup Time for STOP Condition Capacitive Load for Each Bus Line (Note 11) I/O Capacitance (SDA, SCL) Oscillator Stop Flag (OSF) Delay SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB CI/O tOSF (Note 12) (Note 13) 100 CONDITION Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 100 250 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0 400 10 300 1000 300 300 0.9 MIN 100 TYP MAX 400 100 UNITS kHz
ms ms ms ms ms ms ns ns ns ms pF pF ms
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POWER-UP/DOWN CHARACTERISTICS
(TA = -40 C to +85C) (Note 1, Figure 1) PARAMETER Recovery at Power-Up VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) SYMBOL tREC tVCCF tVCCR CONDITIONS (Note 14) 300 0 MIN TYP MAX 2 UNITS ms ms ms
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Limits at -40C are guaranteed by design and are not production tested. SCL only. SDA and SQW/INT. ICCA--SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled. Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC, trickle charger disabled. Using recommended crystal on X1 and X2. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. CB--total capacitance of one bus line in pF. Guaranteed by design. Not production tested. The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V VCC VCCMAX and 1.3V VBACKUP 3.7V. This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.
Note 11: Note 12: Note 13: Note 14:
Figure 1. Power-Up/Down Timing
VCC V PF(MAX) VPF(MIN) t VCCF t VCCR tREC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
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Figure 2. Timing Diagram
Figure 3. Block Diagram
X1 OSCILLATOR AND DIVIDER 1Hz/4.096kHz/8.192kHz/32.768kHz MUX/ BUFFER SQW/INT
X2
1Hz ALARM, TRICKLE CHARGE, AND CONTROL REGISTERS CLOCK AND CALENDAR REGISTERS
"C" VERSION ONLY
VCC VBACKUP POWER CONTROL
CONTROL LOGIC
Dallas Semiconductor
SCL SDA SERIAL BUS INTERFACE AND ADDRESS REGISTER
DS1339
USER BUFFER (7 BYTES)
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PIN DESCRIPTION
PIN SO mSOP 1 -- NAME FUNCTION Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. An external 32.768kHz oscillator can also drive the DS1339. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. Secondary Power Supply. Supply voltage must be held between 1.3V and 3.7V for proper operation. This pin can be connected to a primary cell, such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used in conjunction with the trickle-charge feature. Diodes should not be placed in series between the battery and the VBACKUP input, or improper operation will result. UL recognized to ensure against reverse charging current when used with a lithium battery If a back up supply is not required, VBACKUP must be grounded. Ground. DC power is provided to the device on these pins. Serial Data Input/Output. SDA is the input/output pin for the I C serial interface. The SDA pin is an open-drain output and requires an external pullup resistor. Serial Clock Input. SCL is used to synchronize data movement on the serial interface. Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. The SQW/INT pin is an open-drain output and requires an external pullup resistor. Power Supply. DC power is provided to the device on these pins. No Connection. These pins are unused and must be connected to ground.
2
X1
2
--
X2
3
14
VBACKUP
4 5 6 7 8 --
15 16 1 2 3 4-13
GND SDA SCL SQW/INT VCC N.C.
TYPICAL OPERATING CIRCUIT
VCC VCC CRYSTAL VCC RPU RPU 1 6 CPU 5 X1 SCL X2 2 8 VCC SQW /INT 7
i
DS1339
SDA VBACKUP GND 4 3
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DETAILED DESCRIPTION
The DS1339 serial real-time clock (RTC) is a low-power clock/date device with two programmable time-of-day 2 alarms and a programmable square-wave output. Address and data are transferred serially through an I C bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1339 has a built-in powersense circuit that detects power failures and automatically switches to the backup supply, maintaining time and date operation.
OPERATION
The DS1339 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC is returned to nominal levels. The block diagram in Figure 3 shows the main elements of the serial real-time clock.
OSCILLATOR CIRCUIT
The DS1339 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 4 shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics.
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Table 1. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL 6 MIN TYP 32.768 45 MAX UNITS kHz kW pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
Figure 4. Oscillator Circuit Showing Internal Bias Network RTC
COUNTDOWN CHAIN
CL1
CL2
RTC REGISTERS
X1
X2
CRYSTAL
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 5 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information
DS1339C ONLY
The DS1339C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25C is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
Figure 5. Typical PC Board Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE.
GND
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ADDRESS MAP
Figure 6 shows the address map for the DS1339 registers. During a multibyte access, when the address pointer 2 reaches the end of the register space (10h), it wraps around to location 00h. On an I C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
Figure 6. Timekeeper Registers
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H
0 0 0 0 0 Century 12/24 0 0 0
10 Seconds 10 Minutes AM/PM 10 Hour 0 10 Date 0 10 Year 10 Month 10 Hour 0 0
Seconds Minutes Hour Day Date Month Year Seconds Minutes 10 Hour Hour
Seconds Minutes Hours Day Date Month/ Century Year Alarm 1 Seconds Alarm 1 Minutes Alarm 1 Hours Alarm 1 Day, Alarm 1 Date Alarm 2 Minutes Alarm 2 Hours Alarm 2 Day, Alarm 2 Date A1IE A1F
ROUT0
00-59 00-59 1-12 +AM/PM 00-23 1-7 01-31 01-12 + Century 00-99 00-59 00-59 1-12 + AM/PM 00-23 1-7, 1-31 00-59 1-12 + AM/PM 00-23 1-7, 1-31
A1M1 A1M2 A1M3 12/24
10 Seconds 10 Minutes AM/PM 10 Hour
0AH 0BH 0CH
A1M4 A2M2 A2M3
DY/DT
10 Date 10 Minutes
Day, Date Minutes
12/24
AM/PM 10 Hour
10 Hour
Hour
0DH 0EH 0FH 10H
A2M4 EOSC OSF TCS3
DY/DT 0 0 TCS2 0 0
10 Date RS2 0 TCS0 RS1 0 DS1
Day, Date INTCN 0 DS0 A2IE A2F
ROUT1
Control Status Trickle Charger
TCS1
Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC and VBACKUP falls below the VBACKUP(MIN).
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TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Figure 6 shows the RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the BCD format. The DS1339 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). All hours values, including the alarms, must be re-entered whenever the 12/24-hour mode bit is changed. The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop, and when the address pointer rolls over to zero. The countdown chain is reset whenever the seconds register is written. Write transfers occurs on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. If enabled, the 1Hz square-wave output transitions high 500ms after the seconds data transfer, provided the oscillator is already running.
ALARMS
The DS1339 contains two time of day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the Alarm Enable and INTCN bits of the Control Register) to activate the SQW/INT output on an alarm match condition. Bit 7 of each of the time of day/date alarm registers are mask bits (Table 2). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 2 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to a logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to a logic 1, the alarm is the result of a match with day of the week. The device checks for an alarm match once per second. When the RTC register values match alarm register settings, the corresponding Alarm Flag `A1F' or `A2F' bit is set to logic 1. If the corresponding Alarm Interrupt Enable `A1IE' or `A2IE' is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the SQW/INT) signal. If the BBSQI bit is set to 1, the INT output activates while the part is being powered by VBACKUP. The alarm output remains active until the alarm flag is cleared by the user.
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Table 2. Alarm Mask Bits
DY/DT X X X X 0 1 ALARM 1 REGISTER MASK BITS (Bit 7) A1M4 A1M3 A1M2 A1M1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ALARM RATE Alarm once per second Alarm when seconds match Alarm when minutes and seconds match Alarm when hours, minutes, and seconds match Alarm when date, hours, minutes, and seconds match Alarm when day, hours, minutes, and seconds match
DY/DT X X X 0 1
ALARM 2 REGISTER MASK BITS (Bit 7) A2M4 A2M3 A2M2 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
ALARM RATE Alarm once per minute (00 sec. of every min.) Alarm when minutes match Alarm when hours and minutes match Alarm when date, hours, and minutes match Alarm when day, hours, and minutes match
SPECIAL-PURPOSE REGISTERS
The DS1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.
CONTROL REGISTER (0Eh)
BIT 7
EOSC
BIT 6 0
BIT 5 BBSQI
BIT 4 RS2
BIT 3 RS1
BIT 2 INTCN
BIT 1 A2IE
BIT 0 A1IE
Bit 7: Enable Oscillator (EOSC). This bit when set to logic 0 starts the oscillator. When this bit is set to a logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied. Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to a logic 1 enables the square wave or interrupt output when VCC is absent and the DS1339 is being powered by the VBACKUP pin. When BBSQI is a logic 0, the SQW/INT pin goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
Square-Wave Output Frequency
RS2 0 0 1 1 RS1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz
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DS1339 I C Serial Real-Time Clock Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
2
STATUS REGISTER (0Fh)
BIT 7 OSF BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 A2F BIT 0 A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and date data. This bit is edge triggered and is set to logic 1 when the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage on both VCC and VBACKUP are insufficient to support oscillation. 3) The EOSC bit is turned off. 4) External influences on the crystal (e.g., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the Alarm 2 Flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
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TRICKLE CHARGER REGISTER (10h)
The simplified schematic in Figure 7 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern on 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diode-select (DS) bits (bits 2 and 3) select whether or not a diode is connected between VCC and VBACKUP. The ROUT bits (bits 0 and 1) select the value of the resistor connected between VCC and VBACKUP. Table 3 shows the bit values.
Table 3. Trickle Charger Register (10h)
BIT 7 TCS3 X X X 1 1 1 1 1 1 0 BIT 6 TCS2 X X X 0 0 0 0 0 0 0 BIT 5 TCS1 X X X 1 1 1 1 1 1 0 BIT 4 TCS0 X X X 0 0 0 0 0 0 0 BIT 3 DS1 0 1 X 0 1 0 1 0 1 0 BIT 2 DS0 0 1 X 1 0 1 0 1 0 0 BIT 1 ROUT1 X X 0 0 0 1 1 1 1 0 BIT 0 ROUT0 X X 0 1 1 0 0 1 1 0 FUNCTION Disabled Disabled Disabled No diode, 250W resistor One diode, 250W resistor No diode, 2kW resistor One diode, 2kW resistor No diode, 4kW resistor One diode, 4kW resistor Initial power-up values
The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a 3.3V system power supply is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 (3.3V - 0.7V) / 2kW 1.3mA As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases.
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Figure 7. Programmable Trickle Charger
R1
VCC
250W R2 2kW R3 4kW
VBACKUP
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES CHARGER
1 OF 2 SELECT
1 OF 3 SELECT
TCS3 BIT 7
TCS2 BIT 6
TCS1 BIT 5
TCS0 BIT 4
DS1 BIT 3
DS0 BIT 2
ROUT1 BIT 1
ROUT0 BIT 0
TCS0-3 = TRICKLE CHARGER SELECT = DIODE SELECT DS0-1 ROUT0-1 = RESISTOR SELECT
TRICKLE CHARGE REGISTER
I2C SERIAL DATA BUS
The DS1339 supports the I C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339 2 operates as a slave on the I C bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast mode (400kHz cycle rate) are defined. The DS1339 works in both modes. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 8): Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals.
2
Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
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DS1339 I C Serial Real-Time Clock Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
2
Figure 8. Data Transfer on I2C Serial Bus
Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The DS1339 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (Figure 9). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1339 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. After the DS1339 acknowledges the slave address + write bit, the master transmits a register address to the DS1339. This sets the register pointer on the DS1339, with the DS1339 acknowledging the transfer. The master may then transmit zero or more bytes of 16 of 18
DS1339 I C Serial Real-Time Clock data, with the DS1339 acknowledging each byte received. The address pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1339 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 10). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1339 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The DS1339 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The address pointer is incremented after each byte is transferred. The DS1339 must receive a "not acknowledge" to end a read.
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Figure 9. Data Write--Slave Receiver Mode
slave address S 1101000
R/W
register address (n) A XXXXXXXX A
Data (n) XXXXXXXX A
Data (n+1) XXXXXXXX A
Data (n+x) XXXXXXXX P
0
S - START A - ACKNOWLEDGE P - STOP R/W - READ/WRITE OR DIRECTION BIT
DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE)
Figure 10. Data Read--Slave Transmitter Mode
R/W
slave address S 1101000
Data (n) A XXXXXXXX A
Data (n+1) XXXXXXXX A
Data (n+2) XXXXXXXX A
Data (n+x) XXXXXXXX /A
1
S - START A - ACKNOWLEDGE P - STOP /A - NOT ACKNOWLEDGE R/W - READ/WRITE OR DIRECTION BIT DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE)
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DS1339 I C Serial Real-Time Clock
2
HANDLING, PC BOARD LAYOUT, AND ASSEMBLY
The DS1339C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground. The SO package may be reflowed as long as the peak temperature does not exceed 240C. Peak reflow temperature ( 230C) duration should not exceed 10 seconds, and the total time above 200C should not exceed 40 seconds (30 seconds nominal). Exposure to reflow is limited to 2 times maximum. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020B standard for moisture-sensitive device (MSD) classifications.
PIN CONFIGURATIONS
TOP VIEW TOP VIEW SCL X1 X2 VBACKUP GND VCC
DS1339
SDA
DS1339C
SQW/INT VCC N.C. N.C. N.C. N.C. N.C.
GND VBACKUP N.C. N.C. N.C. N.C. N.C.
SQW/INT SCL SDA
mSOP
SO (300 mils)
CHIP INFORMATION
TRANSISTOR COUNT: 11,325 PROCESS: CMOS
THERMAL INFORMATION
PART SOP SO THETA-JA (C/W) 229 73 THETA-JC (C/W) 39 23 CONDITIONS Typical
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2005 Maxim Integrated Products * Printed USA are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation.

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